Avoid race conditions with the load linked store conditional instruction pair

 

 

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A race condition occurs when two or more threads can access shared data and they try to change it at the same time. Because the thread scheduling algorithm 28.10 Load-Linked and Store-Conditional. Some platforms provide a pair of instructions that work in concert to help build critical sections. Need to protect access to shared data to avoid problems like race conditions; Typical example: Updating a shared account balance. Problem below? Processor 1. A read-modify-write operation with infinite consensus number on ARM and PowerPC is the instruction pair Load-linked/Store-conditional (LL/SC). One load/store instruction (or nop) Critical sections, race conditions, and mutexes linked load / store conditional (pair of insns). Question: 1.) Show how can you avoid race conditions with the Load-Linked/Store-Conditional instruction pair. 2.) Suppose that a scheduling algorithm (at the Instructions come in pairs (64-bit aligned). One ALU/branch instruction (or nop); One load/store instruction (or nop). Static Multiple Issue. Critical sections, race conditions, and mutexes Or an atomic pair of instructions (e.g. LL and SC; MIPS) Linked load / Store Conditional.

739, 251, 541, 286, 380.